Generally, for system-on-chip (SOC) applications, and more specifically, for power management of integrated circuits, it is becoming very important to have a cost-effective process which provides low voltage complementary MOS (CMOS) for logic, intermediate (or medium) voltage devices for analog and high voltage devices for an output high voltage interface stage. These output stages typically require high-speed switches and high package density, which further require low on-resistance (e.g., low Rdson), high package density, higher breakdown voltage (e.g., higher BVdss), and low Miller capacitance.
FIG. 1 illustrates a common high voltage lateral double-diffused metal oxide semiconductor (LDMOS) structure having a substrate 101 with shallow trench isolation (STI) regions 103, high voltage n-type double diffused drain (HVNDDD) region 105, high voltage p-well (PWHV) region 107, and n-doped well (DNWELL) region 109, along with power region 111, source region 113, drain region 115, and gate stack 117. Although the structure is able to operate with high voltages (e.g., voltages higher than 20 V), it is typically unable to achieve sufficiently low on-resistance even when the breakdown voltage is low (e.g., the structure generally cannot achieve less than 6 mOhm-cm2 Rdson even when the BVdss is allowed to drop down to 15 V). Moreover, the integration density of the particular LDMOS structure is not very high, and improvement of the channel density of the LDMOS, which reduces the on-resistance, is subject to certain limitations because the expanded drain region 115 of the LDMOS is formed along the substrate surface. Thus, low efficiency of the power supply results, and a large package with low thermal resistance becomes necessary to realize extremely low on-resistance for the power integrated circuits (ICs).
FIG. 2 illustrates a dual poly-filled LDMOS, which has been proposed to overcome the packing density limitation, as well as the decreasing Rdson, of a common LDMOS structure (e.g., the structure in FIG. 1). The structure in FIG. 2 includes a substrate 201 with a P− doped region 203, an N− doped region 205, an N+ doped region 207, oxide 209, a drain region 211, gate regions 213, oxide spacers 215, source regions 217, body contact regions 219, and STI regions 221. However, as shown by indicator 223, there is no thick oxide that separates the gate regions 213 from the drain region 211, which may, for instance, cause the structure to become vulnerable to high gate to drain capacitances and, thus, cause a substantial decrease of the structure's switching speed. Moreover, indicator 225 depicts the gate oxide integrity (GOI) concern due to the silicon nitride (SiN) residue at the bottom of the oxide spacers 215. Additional concerns may, for instance, include breakdown voltage weak points (e.g., BVdss may remain low) due to the thin gate oxide at the drain side, resulting in lower power efficiency of the LDMOS structure. Furthermore, the LDMOS structure is typically provided as discrete devices (e.g., not integrated with low and medium voltage devices) on integrated circuits, limiting package density of those integrated circuits.
A need therefore exists for an effective integrated trench MOS, and enabling methodology.